Dislocation smt for finfet device

ABSTRACT

A method for performing a stress memorization technique (SMT) a FinFET and a FinFET having memorized stress effects including multi-planar dislocations are disclosed. An exemplary embodiment includes receiving a FinFET precursor with a substrate, a fin structure on the substrate, an isolation region between the fin structures, and a gate stack over a portion of the fin structure. The gate stack separates a source region of the fin structure from a drain region of the fin structure and creates a gate region between the two. The embodiment also includes forming a stress-memorization technique (SMT) capping layer over at least a portion of each of the fin structures, isolation regions, and the gate stack, performing a pre-amorphization implant on the FinFET precursor by implanting an energetic doping species, performing an annealing process on the FinFET precursor, and removing the SMT capping layer.

BACKGROUND

As the semiconductor industry has progressed into nanometer technologyprocess nodes in pursuit of higher device density, higher performance,and lower costs, challenges from both fabrication and design issues haveresulted in the development of three dimensional designs, such as afin-like field effect transistor (FinFET). A typical FinFET isfabricated with a thin “fin” (or fin structure) extending from asubstrate, for example, etched into a silicon layer of the substrate.The channel of the FET is formed in this vertical fin. A gate isprovided over (e.g., wrapping) the fin. It is beneficial to have a gateon both sides of the channel allowing gate control of the channel fromboth sides. Advantages of FinFET devices include reducing the shortchannel effect and higher current flow.

Because of the complexity inherent in nonplanar devices, such asFinFETs, a number of techniques used in manufacturing planar transistorsare not available in manufacturing nonplanar devices. For example,stress-memorization techniques (SMTs) are applied in high-performanceenvironments to improve nMOS devices. By carefully controlling theamorphization and re-crystallization of a planar device channel, theeffects of a stress force applied to the device will remain even afterthe stressor is removed. The stress effects improve charge mobilitythrough the channel, thereby improving device performance. What isneeded is a method of applying SMTs to three-dimensional devices toobtain similar improvements in device performance.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1 is a flowchart of a method for performing a stress-memorizationtechnique on a FinFET precursor according to aspects of the presentdisclosure.

FIGS. 2 a and 2 b are diagrammatic perspective views of a FinFETprecursor undergoing processes according to an embodiment of the presentdisclosure.

FIGS. 3 a and 3 b are diagrammatic cross-sectional views of a FinFETprecursor undergoing processes according to an embodiment of the presentdisclosure.

FIG. 4 is a diagrammatic cross-sectional view of a FinFET precursorundergoing processes according to an embodiment of the presentdisclosure.

FIGS. 5 a and 5 b are a diagrammatic perspective view and a diagrammaticcross-sectional view, respectively, of a FinFET precursor undergoingprocesses according to an embodiment of the present disclosure.

FIGS. 6 a and 6 b are a diagrammatic perspective view and a diagrammaticcross-sectional view, respectively, of a FinFET precursor undergoingprocesses according to an embodiment of the present disclosure.

FIGS. 7 a and 7 b are a diagrammatic perspective view and a diagrammaticcross-sectional view, respectively, of a FinFET precursor undergoingprocesses according to an embodiment of the present disclosure.

FIG. 8 is a diagrammatic perspective view of a FinFET precursorundergoing processes according to an embodiment of the presentdisclosure.

FIG. 9 is a diagrammatic perspective view of a FinFET precursorundergoing processes according to an embodiment of the presentdisclosure.

FIG. 10 is a diagrammatic cross-sectional view of a FinFET precursorundergoing processes according to an embodiment of the presentdisclosure.

DETAILED DESCRIPTION

The present disclosure relates generally to IC device manufacturing, andmore particularly, to a procedure for performing a stress memorizationtechnique (SMT) on a FinFET and to the resulting device.

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. For example, if the device in the figures is turned over,elements described as being “below” or “beneath” other elements orfeatures would then be oriented “above” the other elements or features.Thus, the exemplary term “below” can encompass both an orientation ofabove and below. The apparatus may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein may likewise be interpreted accordingly.

FIG. 1 is a flowchart of a method for performing a stress-memorizationtechnique on a FinFET according to aspects of the present disclosure.FIGS. 2 a, 2 b, 5 a, 6 a, 7 a, 8, and 9 are diagrammatic perspectiveviews of a FinFET precursor according to embodiments of the presentdisclosure. FIGS. 3 a, 3 b, 4, 5 b, 6 b, 7 b, and 10 are sectional viewsof a FinFET precursor according to embodiments of the presentdisclosure. The method 100 and the FinFET precursor 200 are collectivelydescribed with reference to FIG. 1 through FIG. 10. It is understoodthat additional steps can be provided before, during, and after themethod 100, and some of the steps described can be replaced oreliminated for other embodiments of the method.

The method 100 begins at block 102 where a FinFET precursor 200 suitablefor a stress-memorization technique (SMT) is received. As illustrated inFIG. 2 a, the precursor 200 includes a substrate 202. The substrate 202may be a bulk silicon substrate. Alternatively, the substrate 202 maycomprise an elementary semiconductor, such as silicon or germanium in acrystalline structure; a compound semiconductor, such as silicongermanium, silicon carbide, gallium arsenic, gallium phosphide, indiumphosphide, indium arsenide, and/or indium antimonide; or combinationsthereof. Possible substrates 202 also include a silicon-on-insulator(SOI) substrate. SOI substrates are fabricated using separation byimplantation of oxygen (SIMOX), wafer bonding, and/or other suitablemethods.

Some exemplary substrates 202 include an insulator layer. The insulatorlayer comprises any suitable material, including silicon oxide,sapphire, other suitable insulating materials, and/or combinationsthereof. An exemplary insulator layer may be a buried oxide layer (BOX).The insulator is formed by any suitable process, such as implantation(e.g., SIMOX), oxidation, deposition, and/or other suitable process. Insome exemplary FinFET precursors 200, the insulator layer is a component(e.g., layer) of a silicon-on-insulator substrate.

The substrate 202 may include various doped regions depending on designrequirements as known in the art (e.g., p-type wells or n-type wells).The doped regions are doped with p-type dopants, such as boron or BF₂;n-type dopants, such as phosphorus or arsenic; or combinations thereof.The doped regions may be formed directly on the substrate 202, in aP-well structure, in an N-well structure, in a dual-well structure, orusing a raised structure. The semiconductor substrate 202 may furtherinclude various active regions, such as regions configured for an N-typemetal-oxide-semiconductor transistor device and regions configured for aP-type metal-oxide-semiconductor transistor device.

A fin structure 204 is formed on the substrate 202. In some embodiments,the precursor 200 comprises more than one fin structures 204. The finstructure 204 is formed by any suitable process including variousdeposition, photolithography, and/or etching processes. An exemplaryphotolithography process includes forming a photoresist layer (resist)overlying the substrate (e.g., on a silicon layer), exposing the resistto a pattern, performing a post-exposure bake process, and developingthe resist to form a masking element including the resist. The maskingelement is then used to etch the fin structure into the silicon layer.Area not protected by the masking element is etched using reactive ionetching (RIE) processes and/or other suitable processes. In an example,the silicon fin 204 is formed by patterning and etching a portion of thesilicon substrate 202. In another example, the fin structure 204 isformed by patterning and etching a silicon layer deposited overlying aninsulator layer (for example, an upper silicon layer of asilicon-insulator-silicon stack of an SOI substrate). As an alternativeto traditional photolithography, the fin structure 204 can be formed bya double-patterning lithography (DPL) process. DPL is a method ofconstructing a pattern on a substrate by dividing the pattern into twointerleaved patterns. DPL allows enhanced feature (e.g., fin) density.Various DPL methodologies include double exposure (e.g., using two masksets), forming spacers adjacent features and removing the features toprovide a pattern of spacers, resist freezing, and/or other suitableprocesses. It is understood that multiple parallel fin structures 204may be formed in a similar manner.

Suitable materials for forming the fin structure 204 include silicon andsilicon germanium. In some embodiments, the fin structure 204 includes acapping layer disposed on the fins, such as a silicon capping layer. Thefin structure 204 may also include various doped regions. For example,various doped regions can comprise lightly doped source/drain (LDD)regions and source/drain (S/D) regions (also referred to as heavilydoped S/D regions). An implantation process (i.e., a junction implant)is performed to form S/D regions. The implantation process utilizes anysuitable doping species. The doping species may depend on the type ofdevice being fabricated, such as an NMOS or PMOS device. For example,the S/D regions are doped with p-type dopants, such as boron or BF₂;n-type dopants, such as phosphorus or arsenic; and/or combinationsthereof. The S/D regions may comprise various doping profiles. One ormore annealing processes may be performed to activate the S/D regions.The annealing processes comprise rapid thermal annealing (RTA) and/orlaser annealing processes.

Exemplary isolation regions 206 are formed on the substrate 202 toisolate active regions of the substrate 202. The isolation region 206utilizes isolation technology, such as shallow trench isolation (STI),to define and electrically isolate the various regions. The isolationregion 206 comprises silicon oxide, silicon nitride, silicon oxynitride,an air gap, other suitable materials, or combinations thereof. Theisolation region 206 is formed by any suitable process. As one example,the formation of an STI includes a photolithography process, etching atrench in the substrate (for example, by using a dry etching and/or wetetching), and filling the trench (for example, by using a chemical vapordeposition process) with one or more dielectric materials. The trenchesmay be partially filled, as in the present embodiment, where thesubstrate remaining between trenches forms a fin structure. In someexamples, the filled trench may have a multi-layer structure such as athermal oxide liner layer filled with silicon nitride or silicon oxide.

One or more gate structures 208 are formed over the substrate 202,including over a portion of the fin structure 204. The gate structure208 comprises a gate stack and may include a sealing layer and othersuitable structures. The gate stack has an interfacial layer 210, a gatedielectric layer 212, a gate electrode layer 214, and a hard mask layer216. It is understood that the gate stack may comprise additional layerssuch as interfacial layers, capping layers, diffusion/barrier layers,dielectric layers, conductive layers, other suitable layers, and/orcombinations thereof. The interfacial layer 210 of the gate structure208 is formed over the substrate 202 and fin structure 204. Theinterfacial layer 210 is formed by any suitable process to any suitablethickness. An exemplary interfacial layer 210 includes silicon oxide(e.g., thermal oxide or chemical oxide) and/or silicon oxynitride(SiON).

The gate dielectric layer 212 is formed over the interfacial layer 210by any suitable process. The gate dielectric layer 212 comprises adielectric material, such as silicon oxide, silicon nitride, siliconoxynitride, high-k dielectric material, other suitable dielectricmaterial, and/or combinations thereof. Examples of high-k dielectricmaterial includes HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconiumoxide, aluminum oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, othersuitable high-k dielectric materials, and/or combinations thereof.

The gate electrode layer 214 is formed over the gate dielectric layer212 by any suitable process. The gate electrode layer 214 includes anysuitable material, such as polysilicon, aluminum, copper, titanium,tantulum, tungsten, molybdenum, tantalum nitride, nickel silicide,cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys,other suitable materials, and/or combinations thereof.

The hard mask layer 216 is formed over the gate electrode layer 214 byany suitable process. The hard mask layer 216 comprises any suitablematerial, for example, silicon nitride, SiON, SiC, SiOC, spin-on glass(SOG), a low-k film, tetraethylorthosilicate (TEOS), plasma enhanced CVDoxide (PE-oxide), high-aspect-ratio-process (HARP) formed oxide, and/orother suitable material.

The gate stack of the gate structure 208 is formed by any suitableprocess or processes. For example, the gate stack can be formed by aprocedure including deposition, photolithography patterning, and etchingprocesses. The deposition processes include chemical vapor deposition(CVD), physical vapor deposition (PVD), atomic layer deposition (ALD),high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remoteplasma CVD (RPCVD), plasma enhanced CVD (PECVD), plating, other suitablemethods, and/or combinations thereof. The photolithography patterningprocesses include photoresist coating (e.g., spin-on coating), softbaking, mask aligning, exposure, post-exposure baking, developing thephotoresist, rinsing, drying (e.g., hard baking), other suitableprocesses, and/or combinations thereof. Alternatively, thephotolithography exposing process is implemented or replaced by otherproper methods such as maskless photolithography, electron-beam writing,and ion-beam writing. The etching processes include dry etching, wetetching, and/or other etching methods (e.g., reactive ion etching).

The gate structure 208 may further include a gate spacer 218. The gatespacers 218, which are positioned on each side of the gate stack (on thesidewalls of the gate stack), may comprise a dielectric material, suchas silicon nitride, silicon carbide, silicon oxynitride, other suitablematerials, and/or combinations thereof. In some embodiments, the gatespacers 218 are used to offset subsequently formed doped regions, suchas source/drain regions. The gate spacers 218 may further be used fordesigning or modifying the source/drain region (junction) profile.

Referring now to FIG. 2 b, in some embodiments, the FinFET precursor 200includes a substrate 202 with an elevated device body 220 formed overthe surface of the substrate. The elevated device body has source/drainregions 222. In some embodiments, a source/drain region 222 is a sourceregion, and another source/drain region 222 is a drain region. A gateregion 224 is located between the source/drain regions 222. A gatestructure 208 is formed over the gate region 224 of the elevated devicebody 220. In FIG. 2 b, one gate structure 208 is not illustrated tobetter show the underlying gate region 224. Isolation regions 206separate the elevated device bodies 220 from one another.

Once the FinFET precursor 200 is received, it undergoes astress-memorization technique (SMT) in blocks 104-110. The SMT increasescharge mobility through the channel. This leads to dramatic improvementsin device performance. FinFETs having undergone SMT demonstrate higherdrive strength for a given channel size and supply voltage. In brief,the method involves forming an SMT capping layer on the FinFET precursor200. The FinFET 200 undergoes a pre-amorphization implantation (PAI)which injects atoms into the fin structures 204 and disrupts thesemiconductor lattice within the fin structures 204. A thermal annealingis performed for re-crystallization. The SMT capping layer is removed,yet the fin structures 204 retain the stress effects caused by the SMT.These retained effects may be referred to as stress-memorization, thusgiving SMT its name. After the SMT is completed, further FinFETmanufacturing steps may be performed.

Examining the SMT technique in more detail and referring to block 104and FIGS. 3 a and 3 b, an SMT capping layer 300 is formed on the FinFETprecursor 200 covering the fin structure 204, the gate structure 208,and, in some embodiments, an exposed portion of the isolation region206. The capping layer 300 includes silicon nitride or other suitablematerials such as silicon oxide. The capping layer 300 may include asilicon nitride formed by a low pressure CVD (LPCVD), a silicon nitrideformed by a plasma enhanced CVD (PECVD), tetraethyl orthosilicate formedby a CVD process, a silicon oxide formed by a high aspect ratio process(HARP), or another suitable material. In an embodiment, the cappinglayer 300 includes a thickness of about 230 angstroms. In anotherembodiment, the capping layer 300 has a thickness ranging between about200 angstroms and about 2000 angstroms.

Referring to block 106 and FIG. 4, once the capping layer 300 isapplied, a pre- amorphization implantation (PAI) is performed. The PAIinjects atoms into the fin structure 204 in the source/drain (S/D)regions. By introducing energetic doping species, such as Si, Ge, Ar,Xe, BF₂, As, and/or In into the S/D regions, the implantation damagesthe molecular lattice. This creates an amorphous region 400 within thesemiconductor material of the fin structure 204 down to a depth 402. Thedepth 402 is determined according to design specifications and can becontrolled by the PAI process implant energy, implant species,implantation angle and/or implant dosage. The fin structure 204 mayundergo multiple implantations utilizing a variety of energies, species,angles and dosages. In one given embodiment, germanium (Ge) is thespecies implanted, and the implantation energy ranges between about 25KeV and about 30 KeV.

In some embodiments, a patterned photoresist layer may be utilized todefine where the amorphous region 400 is formed and to protect otherregions of the FinFET 200 from implantation damage. For example, thepatterned photoresist layer exposes the fin structures 204, such thatthe source/drain regions are exposed to the PAI process (formingamorphous region 400) while the gate structure 208 (and other portionsof the FinFET 200) are protected from the PAI process. Alternatively, apatterned hard mask layer, such as a SiN or SiON layer, is utilized todefine the amorphous region 400. The patterned photoresist layer or thepatterned hard mask layer may be the hard mask layer 216. Reusing thehard mask layer 216 already in place may reduce cost and manufacturingtime.

At block 108, an annealing process is performed on the FinFET precursor200. When properly performed, the annealing process retains the channelstress effects caused by the capping layer 300 even in the absence ofthe layer 300. The annealing process re-crystallizes the amorphousregions created during the PAI. However, the stress during annealingprevents uniform crystal formation. The re-crystallized region willcontain irregularities such as regions that are locally uniform butexhibit misalignments with other regions. This misalignment may resultin imperfections known as dislocations.

The annealing process may be a rapid thermal anneal (RTA) or amillisecond thermal anneal (MSA), such as a millisecond laser thermalanneal. In one embodiment, the annealing process is implemented in arapid thermal annealing (RTA) tool. In another embodiment, the annealingprocess is applied to the FinFET 200 with an annealing temperatureranging between about 2000° C. and about 1050° C. In another embodiment,the annealing process is applied to the semiconductor structure 200 withan annealing duration ranging between about 5 seconds and about 30seconds. The annealing process may include a long range pre-heat, whichminimizes or even eliminates end of range (EOR) defects. Suitable rangesfor the long range pre-heat range from about 200° C. to about 700° C.,and include other appropriate temperatures and ranges. The long rangepre-heat may be performed for about 50 to about 300 seconds. In aparticular embodiment, the long range pre-heat has a temperature ofabout 550° C. for about 180 seconds.

At block 110, the capping layer 300 is removed from the FinFET 200. Theremoval process may include a wet etching or a dry etching process. Inone example of the FinFET precursor 200 with a silicon nitride cappinglayer 300, the capping layer 300 is removed by an etching processinvolving phosphoric acid. In another example with a silicon oxidecapping layer 300, the silicon oxide is etched away by a hydrofluoricacid (HF) or buffered HF. In another example, the silicon oxide cappinglayer 300 is removed by a CMP process. In some embodiments, it isbeneficial to remove other layers, such as a mask layer, simultaneouslywhile removing the capping layer 300.

Referring to FIGS. 5 a-7 b, due to the stress applied during SMT stepssuch as SMT layer deposition, implantation, and annealing, the finstructures 204 may contain dislocations in the semiconductor lattice.Dislocations begin at a pinchoff point 500. The depth and location ofthe pinchoff point 500 is set according to design specifications and isa function of the pre-amorphization implantation and the annealingprocess. From the pinchoff point, the dislocation propagates along oneor more planes. For clarity in illustrating the planes, the cappinglayer 300 is not shown in FIGS. 5 a-7 b. The planes are described withreference to the longitudinal axis 502 and transverse axis 504 axis ofthe fin structure 204. One exemplary plane is illustrated by plane 506.Plane 506 runs parallel to the longitudinal axis 502 of the finstructure 204 but is directed towards the surface of the substrate 202.In some embodiments, plane 506 corresponds to a 111 Miller index. Such aplane 506 intersects the surface of the substrate 202 at about a55-degree angle. Likewise, plane 508 is similarly parallel to thelongitudinal axis 502 of the fin structure 204 and directed towards thesurface of the substrate 202. In some embodiments, plane 508 intersectsthe surface of the substrate 202 at about a 55-degree angle. A furtherexemplary plane is plane 600, which is parallel to the surface of thesubstrate 202 and parallel to both the longitudinal axis 502 andtransverse axis 504. Plane 700 lies parallel to the transverse axis 504of the fin structure 204 but angles towards the surface of the substrate202. These exemplary planes are not intended to be limiting, and a finstructure 204 may possess dislocations along any one or more of theseplanes.

In some embodiments, after the FinFET precursor 200 undergoes astress-memorization technique, secondary source/drain (S/D) regions maybe formed. To do so, in block 112, the fin structure 204 may bepartially removed as illustrated in FIG. 8. Any suitable amount ofmaterial may be removed. However, the amount removed has an effect onthe presence of memorized stress in the secondary source/drain regionsthat will be formed later. Thus, the depth can be tailored to create orremove desired stress effects and dislocations within the secondary S/Dregions and to control other characteristics of the device channel.

Removing a portion of the fin structure 204 may include forming aphotoresist layer or a capping layer (such as an oxide capping layer)over the FinFET precursor 200, patterning the photoresist or cappinglayer to have openings that expose the S/D regions of the fin structure204, and etching back material from the fin structure 204. In thedepicted embodiment, the fin structure 204 is etched by a dry etchingprocess. Alternatively, the etching process is a wet etching process, orcombination dry and wet etching process. Removal may include alithography process to facilitate the etching process. The lithographyprocess may include photoresist coating (e.g., spin-on coating), softbaking, mask aligning, exposure, post-exposure baking, developing thephotoresist, rinsing, drying (e.g., hard baking), other suitableprocesses, or combinations thereof. Alternatively, the lithographyprocess is implemented or replaced by other methods, such as masklessphotolithography, electron-beam writing, and ion-beam writing. In yetanother alternative, the lithography process could implement nanoimprinttechnology.

Referring to block 114 and FIG. 9, secondary source/drain (S/D) regions900 are formed over the S/D regions of the fin structure 204. Thesecondary S/D regions 900 may be formed by one or more epitaxy orepitaxial (epi) processes, such that Si features, SiGe features, and/orother suitable features can be formed in a crystalline state on the finstructure 204. The epitaxy processes include CVD deposition techniques(e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD(UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. Theepitaxy process may use gaseous and/or liquid precursors, which interactwith the composition of the fin structure 204 (e.g., silicon). Thus, astrained channel can be achieved to increase carrier mobility andenhance device performance. The secondary S/D regions 900 may be in-situdoped. The doping species include p-type dopants, such as boron or BF₂;n-type dopants, such as phosphorus or arsenic; and/or other suitabledopants including combinations thereof. If the secondary S/D regions 900are not in-situ doped, a second implantation process (i.e., a junctionimplant process) is performed to dope the secondary S/D regions 900. Oneor more annealing processes may be performed to activate the S/D regions900. The annealing processes comprise rapid thermal annealing (RTA)and/or laser annealing processes.

The changes to the semiconductor lattice of the fin structure 204 causedby the stress-memory technique may propagate to the secondary S/Dregions 900 which are formed on the fin structure 204. Thus, the S/Dregions 900 may possess stress effects including dislocations along oneor more planes as illustrated in FIG. 10. One exemplary plane isillustrated by plane 506. Plane 506 runs parallel to the longitudinalaxis 502 of the fin structure 204 but is directed towards the surface ofthe substrate 202. In some embodiments, plane 506 corresponds to a 111Miller index. Such a plane 506 intersects the surface of the substrate202 at about a 55-degree angle. Likewise, plane 508 is similarlyparallel to the longitudinal axis 502 of the fin structure 204 anddirected towards the surface of the substrate 202. In some embodiments,plane 508 intersects the surface of the substrate 202 at about a55-degree angle. A further exemplary plane, plane 600 is alignedparallel to the surface of the substrate 202 and parallel to both thelongitudinal axis 502 and transverse axis 504 of the fin structure 204.Plane 700 lies parallel to the transverse axis 504 of the fin structure204 but angles towards the surface of the substrate 202. These exemplaryplanes are not intended to be limiting, and a secondary S/D region 900may possess dislocations along any one or more of these planes.

Referring to block 116, the FinFET 200 may undergo further CMOS or MOStechnology processing to form various features known in the art. Forexample, a cleaning process may be performed to prepare the surface forS/D contact formation (e.g., S/D silicide formation). Subsequentprocessing may form various contacts/vias/lines and multilayerinterconnect features (e.g., metal layers and interlayer dielectrics) onthe substrate 202, configured to connect the various features orstructures of the FinFET 200. The additional features may provideelectrical interconnection to the device including the formed gatestructures. For example, a multilayer interconnection includes verticalinterconnects, such as conventional vias or contacts, and horizontalinterconnects, such as metal lines. The various interconnection featuresmay implement various conductive materials including copper, tungsten,and/or silicide. In one example, a damascene and/or dual damasceneprocess is used to form a copper related multilayer interconnectionstructure.

Thus, the present invention provides a method for performing a stressmemorization technique (SMT) on a FinFET and provides a FinFET withstress effects including multi-planar dislocations. In one embodiment,the method includes: receiving a FinFET precursor comprising: asubstrate; a fin structure formed on the substrate; an isolation regionformed on the substrate and isolating the fin structure; and a gatestack formed over a portion of the fin structure, thereby separating asource region of the fin structure from a drain region of the finstructure and creating a gate region therebetween; forming astress-memorization technique (SMT) capping layer over at least aportion of each of the fin structures, the isolation region, and thegate stack; performing a pre-amorphization implant on the FinFETprecursor by implanting an energetic doping species; performing anannealing process on the FinFET precursor; and removing the SMT cappinglayer.

In a further embodiment, the semiconductor device comprises: a substratehaving a surface; a fin structure formed over the surface of thesubstrate, the fin structure having an elongated body, a longitudinalaxis, and a transverse axis parallel to the surface of the substrate,wherein the fin structure has a dislocation; an isolation region formedon the surface of the substrate and isolating the fin structure; and agate stack formed over a portion of the fin structure, therebyseparating a source region of the fin structure and a drain region ofthe fin structure and creating gate region of the fin structuretherebetween.

In yet another embodiment, the semiconductor device comprises: asubstrate having a surface; an elevated device body formed over thesurface of the substrate, the elevated device body comprising a drainregion, a source region, and a gate region located between the drain andsource regions, wherein the elevated device body has a longitudinal axisand a transverse axis parallel to the surface of the substrate; adislocation formed within the elevated device body; an isolation regionformed on the surface of the substrate and isolating the elevated devicebody; and a gate stack formed over a portion of the gate region of theelevated device body.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of manufacturing a semiconductor devicecomprising: receiving a FinFET precursor comprising: a substrate; a finstructure formed on the substrate; an isolation region formed on thesubstrate and isolating the fin structure; and a gate stack formed overa portion of the fin structure, thereby separating a source region ofthe fin structure from a drain region of the fin structure and creatinga gate region of the fin structure therebetween; forming astress-memorization technique (SMT) capping layer over at least aportion of each of the fin structure, the isolation region, and the gatestack; performing a pre-amorphization implant on the FinFET precursor byimplanting an energetic doping species; performing an annealing processon the FinFET precursor; and removing the SMT capping layer.
 2. Themethod of claim 1, the method further comprising: removing a portion ofthe fin structure; and thereafter forming a secondary source/drainregion on top of the fin structure.
 3. The method of claim 2, whereinthe removing the portion of the fin structure is performed to a specificdepth, and wherein the specific depth is selected to control thepresence of stress effects in the secondary source/drain region.
 4. Themethod of claim 1, the method further comprising performing amanufacturing process on the FinFET precursor following removing the SMTcapping layer.
 5. A semiconductor device comprising: a substrate havinga surface; a fin structure formed over the surface of the substrate, thefin structure having an elongated body, a longitudinal axis, and atransverse axis parallel to the surface of the substrate, wherein thefin structure has a dislocation; an isolation region formed on thesurface of the substrate and isolating the fin structure; and a gatestack formed over a portion of the fin structure, thereby separating asource region of the fin structure and a drain region of the finstructure and creating gate region of the fin structure therebetween. 6.The semiconductor device of claim 5, wherein: the dislocation is a firstdislocation; the semiconductor device further comprises a seconddislocation formed within the fin structure; and the first dislocationand the second dislocation are not coplanar.
 7. The semiconductor deviceof claim 5, wherein the dislocation is parallel to the surface of thesubstrate.
 8. The semiconductor device of claim 5, wherein thedislocation is parallel to the longitudinal axis of the correspondingfin structure and extends in the direction of the substrate.
 9. Thesemiconductor device of claim 5, wherein the dislocation is parallel tothe transverse axis of the corresponding fin structure and extends inthe direction of the substrate.
 10. The semiconductor device of claim 5,wherein the fin structure comprises a first fin portion and a second finportion and wherein the second fin portion is a secondary source/drainregion.
 11. The semiconductor device of claim 10, wherein thedislocation is formed entirely within the second fin portion.
 12. Thesemiconductor device of claim 10, wherein the dislocation is formedwithin the first fin portion and the second fin portion.
 13. Asemiconductor device comprising: a substrate having a surface; anelevated device body formed over the surface of the substrate, theelevated device body comprising a drain region, a source region, and agate region located between the drain and source regions, wherein theelevated device body has a longitudinal axis and a transverse axisparallel to the surface of the substrate; a dislocation formed withinthe elevated device body; an isolation region formed on the surface ofthe substrate and isolating the elevated device body; and a gate stackformed over a portion of the gate region of the elevated device body.14. The semiconductor device of claim 13, wherein: the dislocation is afirst dislocation; the semiconductor device further comprises a seconddislocation formed within the elevated device body; the firstdislocation and the second dislocation are formed within the same of thedrain region, the source region, and the gate region of the elevateddevice body; and the first dislocation and the second dislocation arenot coplanar.
 15. The semiconductor device of claim 13, wherein thedislocation is parallel to the surface of the substrate.
 16. Thesemiconductor device of claim 13, wherein the dislocation is parallel tothe longitudinal axis of the corresponding elevated device body andextends in the direction of the substrate.
 17. The semiconductor deviceof claim 13, wherein the dislocation is parallel to the transverse axisof the corresponding elevated device body and extends in the directionof the substrate.
 18. The semiconductor device of claim 13, wherein thedislocation is formed entirely within the source region of the elevateddevice body.
 19. The semiconductor device of claim 13, wherein thedislocation is formed entirely within the drain region of the elevateddevice body.
 20. The semiconductor device of claim 13, wherein thedislocation is formed within the gate region and one of the sourceregion and the drain region of the elevated device body.